1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of using damaged areas of a wafer for process qualifications and experiments, and a system for accomplishing same.
2. Description of the Related Art
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting wafer. By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting wafer 11 comprised of doped-silicon. The wafer 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the wafer 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown).
In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes, along with various ion implant and heating processes, are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the wafer. These conductive interconnections allow electrical signals to propagate between the transistors formed above the wafer.
As shown in FIG. 2, a plurality of die 26 are typically formed above the wafer 11. The die 26 define the area of the wafer 11 where production integrated circuit devices, e.g., microprocessors, ASICs, memory devices, will be formed. The size, shape and number of die 26 per wafer 11 depend upon the type of device under construction. For example, several hundred die 26 may be formed above an 8-inch diameter wafer 11. The wafer 11 may also have an alignment notch 17 that is used to provide relatively rough alignment of the wafer 11 prior to performing certain processes, e.g., an alignment process prior to performing an exposure process in a stepper tool.
During the course of manufacturing integrated circuit devices on the wafer 11, it is not uncommon for one or more problems to arise such that one or more die 26 are, for all practical purposes, rendered useless. That is, for a variety of reasons, it is determined that integrated circuit devices suitable for their intended use cannot be formed on such useless die. Such useless die are sometimes referred to as xe2x80x9cbadxe2x80x9d die, as opposed to xe2x80x9cgoodxe2x80x9d die where useful integrated circuit devices may be formed. The die 26 may become useless due to a variety of reasons, e.g., errors in patterning one or more layers, misalignment of layers, incomplete line formation, particle contamination, etc. Traditionally, even after the bad die are identified, they are subjected to the same subsequent process operations as are the good die on the wafer 11. Depending upon the number of bad die on the wafer 11, they may consume a great deal of very valuable plot space on the wafer 11.
Traditionally, test wafers are used to qualify various processes and/or to conduct experiments as to the acceptability of new processes or proposed process changes. These test wafers tend to be expensive, and consume valuable and scarce processing resources. Moreover, production die 26 are not produced on the test wafer, i.e., the test wafers are not used to produce final integrated circuit products. Accordingly, process yields may be reduced. Additionally, as the size of the wafers continues to increase, e.g., from 8-inch wafers to 12-inch wafers, the use of such test wafers becomes more expensive. What is desired is a method that makes use of otherwise wasted plot space occupied by the bad die on a wafer 11.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
In general, the present invention is directed to a method of using damaged areas of a wafer for process qualifications and experiments, and a system for accomplishing same. In one illustrative embodiment, the method disclosed herein comprises providing a wafer, forming a plurality of die above the wafer, identifying a plurality of good die and at least one non-useful die from the plurality of die, and performing a test process on the at least one non-useful die on the wafer but not on the good die.
In another aspect, the present invention is directed to a system that comprises a metrology tool for receiving a wafer having a plurality of die formed thereabove and identifying a plurality of good die and at least one non-useful die on a wafer from the plurality of die formed above the wafer, and a process tool for performing a test process on the at least one non-useful die on the wafer but not on the plurality of good die. In some embodiments, a controller may be provided to assist in identifying the non-useful die or in performing that operation alone.